1. Field of the Invention
The present invention relates generally to clocking circuits, and in particular, to methods and apparatus for a refresh clock generator.
2. Description of the Related Art
Flash Electrically Erasable Programmable Read-Only Memory (flash memory or Flash EEPROM memory) is a nonvolatile memory including EEPROM cells, wherein an EEPROM cell retains a programmed value, such as a logical one or a logical zero, even when power is removed from the circuitry. Flash memory conventionally utilizes a floating gate MOS field effect transistor having a drain region, a source region, a floating gate, and a control gate. Conductors are respectively connected to the drain, source, and control gate for applying signals to the transistor.
A standby charge pump is conventionally utilized to generate a wordline voltage for a read operation. The sustained capacitance can be made up from gates, junctions and wells. However, the capacitance charge tends to leak over time, such as when in a power down or stand by mode. For example, the reverse bias junction diode and well have leakage current, where the leakage current is temperature dependent. At times it may be necessary to periodically re-fill the sustaining capacitor for the leaked charge after a period of time or when coming out of a power down or stand by mode, wherein the timing can be set by a refresh clock generator.
Because of the leakage, and resulting low wordline voltage, conventionally the first read after coming out of a power-down or standby mode may disadvantageously fail. While there have been attempts to compensate for such temperature dependencies in leakage current using a variety of circuits, these compensating circuits often rely on a resistor having a negative temperature coefficient that forms the resistor portion of an RC (resistor-capacitor) circuit used in a clocked circuit to control the clock period. However, it is difficult to fabricate a resistor from polysilicon having the desired large and controllable negative temperature coefficient using many common processes, and so such a compensation circuit may not be practical to implement for many applications.